From: Chad Goodman <cgoodman@HP-EliteBook-2730p.(none)>
Date: Mon, 10 Dec 2012 02:53:12 +0000 (-0800)
Subject: CPU: support 2.1 GHz
X-Git-Url: https://projects.ziggy471.com/git/gitweb.cgi?p=ziggy471-sgs3-jb.git;a=commitdiff;h=eed2b9d35509a092acb3a2e752afdae07bdc0c55

CPU: support 2.1 GHz

Signed-off-by: Ziggy <ziggy@tardis.(none)>
---

--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -515,8 +515,10 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1250000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1250000 },
 	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1262500 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(23), 1262500 },
-	{ 1, {  1890000, HFPLL, 1, 0, 0x40 }, L2(23), 1300000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1262500 },
+	{ 1, {  1890000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
+	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
+	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
 	{ 0, { 0 } }
 };
 
@@ -546,8 +548,10 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1200000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1200000 },
 	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1250000 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(23), 1275000 },
-	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(23), 1300000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1275000 },
+	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
+	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
+	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
 	{ 0, { 0 } }
 };
 
@@ -577,8 +581,10 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1150000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1175000 },
 	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1200000 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(23), 1250000 },
-	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(23), 1300000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1250000 },
+	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
+	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
+	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
 	{ 0, { 0 } }
 };
 
@@ -608,8 +614,10 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1125000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1175000 },
 	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1200000 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(23), 1250000 },
-	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(23), 1300000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1250000 },
+	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
+	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
+	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
 	{ 0, { 0 } }
 };
 
@@ -1223,7 +1231,7 @@ static void __init hfpll_init(struct sca
 }
 
 /* Voltage regulator initialization. */
-static void __init regulator_init(int set_vdd)
+static void regulator_init(int set_vdd)
 {
 	int cpu, ret;
 	struct scalable *sc;
@@ -1254,7 +1262,7 @@ static void __init regulator_init(int se
 }
 
 /* Set initial rate for a given core. */
-static void __init init_clock_sources(struct scalable *sc,
+static void init_clock_sources(struct scalable *sc,
 				      struct core_speed *tgt_s)
 {
 	uint32_t regval;
@@ -1284,7 +1292,7 @@ static void __init init_clock_sources(st
 	sc->first_set_call = true;
 }
 
-static void __init per_cpu_init(void *data)
+static void per_cpu_init(void *data)
 {
 	struct acpu_level *max_acpu_level = data;
 	int cpu = smp_processor_id();
@@ -1310,9 +1318,9 @@ static void __init bus_init(unsigned int
 }
 
 #ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][34];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE];
 
-static void __init cpufreq_table_init(void)
+static void cpufreq_table_init(void)
 {
 	int cpu;
 
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -353,7 +353,10 @@ static inline unsigned int cpufreq_quick
 #define LOW_MAX_FREQ_LIMIT 1188000
 
 #define MIN_FREQ_LIMIT 384000
-#define MAX_FREQ_LIMIT 1900000
+#define MAX_FREQ_LIMIT 2106000
+	#define FREQ_TABLE_SIZE		38
+	#define FREQ_TABLE_SIZE_OFFSET	6
+	#define FREQ_STEPS		30
 
 enum {
 	SET_MIN = 0,